1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of integrated circuits and, in particular, to the provision of layouts of integrated circuits including test cells.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include, in particular, field effect transistors. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in a dielectric material, for example, by means of damascene techniques. The electrically conductive metal lines may be provided in a plurality of metal layers that are arranged above each other over a substrate in and on which the circuit elements are formed. Metal lines in different metal layers may be electrically connected with each other by means of contact vias that are filled with metal and are provided in via layers that are arranged between the metal layers. Further electrically conductive features, such as contacts and vias filled with an electrically conductive material, may be provided for providing an electrical connection between the metal lines in the lowest metal layer and the circuit elements.
Due to the complexity of modern integrated circuits, in the design of integrated circuits, techniques of electronic design automation are typically employed. Techniques of electronic design automation may include the creation of a user specification that defines the functionality of the integrated circuit. The user specification may be the basis for the creation of a register transfer level description that models the integrated circuit in terms of a flow of signals between hardware registers and logical operations performed on those signals. The register transfer level description of the integrated circuit may then be used for the physical design of the integrated circuit, wherein a layout of the integrated circuit is created. The layout may include layer layout information for a plurality of layers of the integrated circuit, and it may be used for forming one or more reticles (sometimes also denoted as “photomasks”) for each of the layers of the integrated circuit. The reticles may then be employed for patterning materials in the manufacturing of the integrated circuit by means of photolithography processes.
Before the photomasks are manufactured by means of techniques such as electron beam lithography, a processing of the layout may be performed, as described in the following with reference to FIG. 1. At 101, the layout is received. The layout may be received in the form of an artwork file provided by a layout tool, for example, as a GDSII file.
At 102, dummy patterns may be inserted into the layout. Dummy patterns may be inserted into the layout between regions of the layout that include target features for providing functional circuit features of the integrated circuit. Dummy patterns may be included into regions of the integrated circuit wherein there is a relatively small density of functional circuit features. This may help to maintain a density of circuit features in a range that is advantageous with respect to a manufacturability of the integrated circuit.
At 103, a bias may be applied and/or a retargeting of the layout may be performed. In doing so, shapes of target features in the layout that define shapes of features to be formed on a semiconductor wafer in a photolithography process may be amended for improving a manufacturability of the integrated circuit.
At 104, an insertion of sub-resolution assist features (SRAFs) may be performed. SRAFs may be provided on the reticle in addition to printing reticle features which are employed for forming photoresist features of the photoresist mask. SRAFs may be small reticle features which may have a bar shape and which are provided on the reticle in the vicinity of the printing reticle features. When the reticle is used in a photolithography process, typically no photoresist features corresponding to the SRAFs are formed in the photoresist mask. However, the presence of SRAFs may reduce a sensitivity of the photolithography process with respect to variations of parameters of the photolithography process, which may include, in particular, a focus of the projection and a dose of the radiation used for projecting the reticle to the photoresist.
An inclusion of SRAFs may be performed in accordance with rule-based techniques or model-based techniques. In model-based techniques, an optical model that may be used for a simulation of a photolithography process may be provided. The simulation of the photolithography process may include a simulation of the formation of an aerial image by the optical system of the photolithography tool and/or a simulation of the behavior of the photoresist. The simulation may be employed in an optimization process wherein SRAFs are included into the layout.
In rule-based techniques, a set of rules, which are denoted as “recipes,” define the inclusion of SRAFs in dependence of patterns of target features in the layout.
At 105, an optical proximity correction (OPC) and an adjustment of SRAFs may be performed. In OPC techniques, shapes of reticle features that are provided on a reticle may be modified compared to shapes of target features that are to be formed in a photoresist mask that is formed from a layer of photoresist on the wafer in the photolithography process. OPC may help to compensate for image errors in the projection of the reticle to the photoresist and/or other process errors.
Techniques for performing OPC include rule-based OPC processes and model-based OPC processes. In rule-based OPC processes, edges of reticle features may be moved relative to edges of target features and/or additional polygons may be added to the reticle features. The movement of edges and/or the addition of polygons may be performed on the basis of a set of rules that is defined by a rule script. The rules may include, for example, an addition of serifs at convex corners of reticle features, a removal of portions of reticle features at concave corners or a modification of a size of reticle features, for example, an increase of a size of reticle features that are provided for forming photoresist features employed in the formation of isolated contact vias.
In model-based OPC techniques, a simulation of a photolithography process may be performed, and a modification of the shapes of the reticle features compared to the shapes of the target features may be performed on the basis of results of the simulation so that a better agreement between the shapes of the photoresist features in the photomask with the shapes of the target features is obtained.
The adjustment of the SRAFs may include an adjustment of sizes of the SRAFs in order to avoid a printing of patterns corresponding to the SRAFs in the photoresist.
At 106, the layout as amended at 102, 103 and 105 may be output for the reticle formation.
For monitoring the performance of processes used for the formation of the reticles, such as electron beam lithography and photolithography processes wherein the reticles are used for patterning a photoresist layer on a wafer, various measurements may be performed, which may include standard measurements of critical dimensions and measurements for long term monitoring of critical dimensions that may be used for wafer critical dimension uniformity (CDU) measurement. Results of wafer CDU measurements may be fed back to a photolithography tool such as, for example, a scanner, for intra-field CDU correction in photolithography processes performed at wafers.
Furthermore, measurements of critical dimensions may be performed for purposes of dose mapping in reticle formation, and for providing critical dimension correction maps for electron beam lithography tools that are used for the manufacturing of the reticle. In such measurements, dimensions of test features on a reticle and/or test features on a wafer that are formed using the reticle may be measured.
The test features may be provided in test cells, which may be provided in a die area of a reticle for forming in-die test cells which are arranged between functional circuit features of an integrated circuit. The test cells may include arrangements of test features for performing various measurements, as described above.
In advanced technology nodes, for example in the 28 nm technology node or below, only relatively small amounts of space may be available between circuit features, which may be as small as 9×3.5 μm2 or 4×2 μm2 in front-end-of-line (FEOL) layers of the integrated circuit, and 4×4 μm2 in back-end-of-line (BEOL) layers, and the possibilities for inclusion of test cells into middle-of-line (MOL) layers of the integrated circuit may be even more limited.
Embodiments disclosed herein provide methods that may allow an inclusion of test cells into layouts of integrated circuits formed in accordance with advanced technology nodes.
Furthermore, embodiments disclosed herein provide methods for an inclusion of test cells into middle-of-line layers of the integrated circuit, such as a via-zero layer, wherein vias providing electrical connections between a metal-one layer (sometimes also denoted as “first metal layer” or “1X metal layer”) of the integrated circuit, which is the lowest metal layer of the integrated circuit, and contacts for providing electrical connections to circuit features such as field effect transistors are formed.